The present invention relates to generally to digital equipment, and more particularly to a method and apparatus for monitoring a synchronization circuit to ensure proper operation of the circuit.
In many digital systems, it is often necessary to receive asynchronously appearing pulses, and to synchronize those pulses with an internal clock (i.e., a periodic pulse train). An example of a synchronization circuit may be found in U.S. Pat. No. 4,700,346.
There are occasions, however, when a synchronization circuit will fail to respond to a received input pulse. For example, when the received input pulse is shorter than the sampling period of the synchronizer no synchronized representation will be produced. Also, when the pulse rate of the input signal is higher than the synchronization rate the synchronizer may fail to respond. Of course, the synchronizer itself may fail, causing it to ignore input events. These are all circumstances which could create problems if not detected.